1. Field of the Invention
The present invention relates to a flip-flop circuit and more particularly to the flip-flop circuit which is incorporated in a semiconductor memory device or a variety of semiconductor integrated-circuit (IC) device or a like.
2. Description of the Related Art
There has been proposed by Akeyoshi et al. such a flip-flop circuit which includes a smaller number of elements by utilizing functionality of a negative differential resistance element. This type of flip-flop circuit is disclosed in Japanese Laid-Open Patent Application No. Hei-9-162705.
The configuration and operations of this prior art flip-flop circuit are briefly described with reference to FIG. 5. FIG. 5 shows the circuit diagram of a conventional D flip-flop circuit. This prior art circuit includes negative differential resistance elements 2, 12, 18 and 19 having a terminal for controlling an element current value, other negative differential resistance elements 1 and 13, and series circuits 8, 16, and 20 consisting of pairs of the negative differential resistance elements 1 and 2, 12 and 13, and 18 and 19 respectively.
Terminals SS1, SS2, and SS6 are grounded, while power supply terminals DD1 and DD2 of the series circuits 8 and 16 respectively are supplied with a vibration voltage synchronized with a clock signal CLK. A power supply terminal DD6 of the series circuit 20, on the other hand, is supplied with a constant voltage. To a control terminal of the negative differential resistance elements 2 and 12 is applied an input signal, so that an output of this circuit as a whole is placed at an output terminal OUT5 of the series circuit 20.
FIGS. 6A, 6B and 6C show load curves indicating operations of the series circuit 8. Here, the negative differential resistance elements 1 and 2 are set to have such characteristics that when the input signal is at a high level (hereafter abbreviated as High), the negative differential resistance element 2, a peak current of which can be controlled with an input signal level, may have a larger peak current than that of the negative differential resistance element 1 and, when the input signal is at a low level (hereinafter abbreviated as Low) on the other hand, the negative differential resistance element 2 may have a smaller peak current than that of the negative differential resistance element 1.
With this, when the clock signal CLK is at Low, a potential of an output terminal OUT1 stays at Low irrespective of a level of the input voltage as shown in FIG. 6A. When the clock signal CLK becomes High, a potential at the terminal DD1 rises, to provide a load curve shown in either FIG. 6B or FIG. 6C so that the potential at the output terminal OUT1 may enter a Low-High bi-stable state. When the input signal is at High and the negative differential resistance element 2 has a larger peak current than the negative differential resistance element 1 as shown in FIG. 6B, the output terminal OUT1 becomes Low and, when the input signal is at Low, on an other hand, as shown in FIG. 6C, the output terminal OUT1 becomes High. Once a voltage level of the output terminal OUT1 is determined in state, this state is held as long as the clock signal CLK remains at High, even when the input signal changes in level. That is, an inverted value of the input signal at a leading edge of the clock signal CLK appears at the output terminal OUT1.
For the series circuit 16, on the other hand, the negative differential resistance elements 12 and 13 are set to have such characteristics that when the input signal is at High, the negative differential resistance element 12 may have a larger peak current than that of the negative differential resistance element 13 and, when the input signal is at Low, may have a smaller one; with this, at the leading edge of the clock signal CLK, a signal having a same phase as the input signal is output at an output terminal OUT2 and held as is until the clock signal CLK rises completely.
FIGS. 7A, 7B and 7C show load curves of the series circuit 20. The series circuit 20 is driven by a power supply which supplies a constant voltage. As shown in FIG. 7A, when both control terminals Yl and Y2 of the negative differential resistance elements 18 and 19 respectively are at Low, a potential of the output terminal OUT5 performs a bi-stable latch operation. If, in this case, only the control terminal Y1 of the negative differential resistance element 18 becomes High in potential, as shown in FIG. 7B, the output voltage also becomes High and, even when the control terminal Y1 gets back to Low subsequently, the output stays at High. When, once the control terminal Y2 of the negative differential resistance element 19 becomes High in potential, as shown in FIG. 7C, the output voltage becomes Low and, even when the control terminal Y2 gets back to Low subsequently, the output voltage stays at Low.
As shown in FIG. 5, the output terminal OUT1 in the series circuit 8 is connected to the control terminal Y2 of the negative differential resistance element 19 in series circuit 20, while the output terminal OUT2 in the series circuit 8 is connected to the control terminal Y1 of the negative differential resistance element 18 in the series circuit 20. When the input voltage is at High, at the leading edge of the clock signal CLK, the output of the series circuit 16 becomes High and that of the series circuit 8 becomes Low, so that the output terminal OUT1 of the series circuit 20 becomes High. Even if the input signal changes in level when the clock signal CLK is at High, states of the output terminals OUT1 and OUT2 both remain unchanged, thus holding an output potential as is.
Further, even when the clock signal CLK falls in potential and so the output terminals OUT1 and OUT2 both become Low, the series circuit 20 holds the output voltage as is. Similarly, with the input signal held at Low, when the clock signal CLK rises in potential, the output terminal OUT5 becomes Low and remains as is until the clock signal CLK rises next time. That is, this circuit acts as a D flip-flop circuit which is triggered at a positive-going edge.
If, in this circuit, a resonant tunnel diode is employed as the negative differential resistance elements 1 and 13 and a parallel-connected element consisting of the resonant tunnel diode and a Field Effect Transistor (FET) is employed as the negative differential resistance elements 2, 12, 18, and 19 having the terminal for controlling the element current value, the number of elements required can be reduced to ten, thus providing a remarkable decrease as compared to a circuit which includes only FETS.
Thus, in the prior art example, by utilizing a functionality of the negative differential resistance elements, the number of elements required can be reduced remarkably as compared to a case where only transistors are employed to make up the circuit. Semiconductor memory devices and IC devices have recently been needed to be even higher in integration density and even larger in scale. With this, it is necessary to reduce a number of required elements and area of the flip-flop circuit which is incorporated in large number in such the semiconductor memory device and IC device. Its power consumption also is desired to be less as much as possible.